1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, to a semiconductor substrate having a dielectric isolation structure and a method of manufacturing the same.
2. Description of the Prior Art
In conventional techniques for monolithically integrating a control circuit element and a high-breakdown-voltage, large-current power element having a current path from the upper surface of a semiconductor substrate to the lower surface thereof, as a technique for forming a power element formation region using an epitaxial method, a bonded substrate using the element isolation method as shown in FIGS. 1A to 1E and FIG. 2 is proposed in the CICC of IEEE 1987, and Japanese Patent Laid-Open No. 3-34347 (corresponding to U.S. Pat. No. 4,908,328).
An example of the conventional technique will be described hereinafter with reference to FIGS. 1A to 1E.
As shown in FIG. 1A, oxide films 3 are formed on one surface of an n-type first monocrystalline silicon substrate 1 having an n+-type heavily doped impurity layer 2, and one surface of an n+-type second monocrystalline silicon substrate 4 having a higher impurity concentration than that of the first monocrystalline silicon substrate 1, respectively.
As shown in FIG. 1B, the surfaces on which the oxide films 3 are formed are bonded to each other by a bonding technique. (Reference numeral 5 denotes a bonding surface in FIG. 1B.)
Subsequently, as shown in FIG. 1C, etching is performed from the upper surface of the first monocrystalline silicon substrate 1 exceeding the bonding surface 5 so as to reach the second monocrystalline silicon substrate 4. (Reference numeral 6 denotes an epitaxial layer formation region in FIG. 1C.)
As shown in FIG. 1D, an n-type monocrystalline silicon epitaxial layer 7 having an optimal concentration for formation of a power element is grown on the etched surface.
Thereafter, as shown in FIG. 1E, a trench groove 27 which reaches the oxide film 3 present on the bonding surface 5 is formed by the anisotropic reactive ion etching (RIE) method. After an oxide film 3 is formed inside the trench groove 27, polysilicon 28 is filled in the trench groove 27, thereby isolating the dielectric.
With this arrangement, a vertical power element can be formed in the monocrystalline silicon epitaxial layer 7 (power element formation region 16) electrically connected to the second monocrystalline silicon substrate 4, and a control circuit element can be formed in a region (control circuit element formation region) 17 dielectrically isolated by the oxide film 3 present on the bonding surface 5 and the oxide film 3 formed inside the trench groove 27 (see FIG. 1E).
Another example of the conventional technique which is difference from that of the conventional technique shown in FIGS. 1A to 1E will be described with reference to FIG. 2.
Note that, in FIG. 2, reference numerals 29 and 30 denote a p-type isolation diffusion layer and an n+-type monocrystalline epitaxial layer, respectively, and other reference numerals denote the same parts in the conventional example shown in FIGS. 1A to 1E.
In this example of the conventional technique, as shown in FIG. 2, the p-type isolation diffusion layer 29 which reaches an oxide film 3 present on a bonding surface 5 is formed from the upper surface of an n-type first monocrystalline silicon substrate 1. A control circuit element and a power element are isolated from each other by a p-n junction isolation.
When a power element having a current path from the upper surface of a silicon substrate to the lower surface thereof and a control circuit element are monolithically integrated, isolation between elements by a p-n junction as in FIG. 2 has a drawback in that it is greatly difficult to realize a high breakdown voltage.
According to the conventional techniques shown in FIGS. 1A to 1E and FIG. 2, after the power element formation region 16 is formed using an epitaxial method, the control circuit element formation region 17 is isolated from the power element formation region 16. For this reason, the trench groove 27, the oxide film 3, and the polysilicon 28 need to be formed (see FIG. 1E), or the isolation diffusion layer 29 needs to be formed (see FIG. 2). This complicates the manufacturing processes, and also results in high cost.